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  1. // Copyright 2018 The Go Authors. All rights reserved.
  2. // Use of this source code is governed by a BSD-style
  3. // license that can be found in the LICENSE file.
  4. // Package cpu implements processor feature detection for
  5. // various CPU architectures.
  6. package cpu
  7. // Initialized reports whether the CPU features were initialized.
  8. //
  9. // For some GOOS/GOARCH combinations initialization of the CPU features depends
  10. // on reading an operating specific file, e.g. /proc/self/auxv on linux/arm
  11. // Initialized will report false if reading the file fails.
  12. var Initialized bool
  13. // CacheLinePad is used to pad structs to avoid false sharing.
  14. type CacheLinePad struct{ _ [cacheLineSize]byte }
  15. // X86 contains the supported CPU features of the
  16. // current X86/AMD64 platform. If the current platform
  17. // is not X86/AMD64 then all feature flags are false.
  18. //
  19. // X86 is padded to avoid false sharing. Further the HasAVX
  20. // and HasAVX2 are only set if the OS supports XMM and YMM
  21. // registers in addition to the CPUID feature bit being set.
  22. var X86 struct {
  23. _ CacheLinePad
  24. HasAES bool // AES hardware implementation (AES NI)
  25. HasADX bool // Multi-precision add-carry instruction extensions
  26. HasAVX bool // Advanced vector extension
  27. HasAVX2 bool // Advanced vector extension 2
  28. HasBMI1 bool // Bit manipulation instruction set 1
  29. HasBMI2 bool // Bit manipulation instruction set 2
  30. HasERMS bool // Enhanced REP for MOVSB and STOSB
  31. HasFMA bool // Fused-multiply-add instructions
  32. HasOSXSAVE bool // OS supports XSAVE/XRESTOR for saving/restoring XMM registers.
  33. HasPCLMULQDQ bool // PCLMULQDQ instruction - most often used for AES-GCM
  34. HasPOPCNT bool // Hamming weight instruction POPCNT.
  35. HasRDRAND bool // RDRAND instruction (on-chip random number generator)
  36. HasRDSEED bool // RDSEED instruction (on-chip random number generator)
  37. HasSSE2 bool // Streaming SIMD extension 2 (always available on amd64)
  38. HasSSE3 bool // Streaming SIMD extension 3
  39. HasSSSE3 bool // Supplemental streaming SIMD extension 3
  40. HasSSE41 bool // Streaming SIMD extension 4 and 4.1
  41. HasSSE42 bool // Streaming SIMD extension 4 and 4.2
  42. _ CacheLinePad
  43. }
  44. // ARM64 contains the supported CPU features of the
  45. // current ARMv8(aarch64) platform. If the current platform
  46. // is not arm64 then all feature flags are false.
  47. var ARM64 struct {
  48. _ CacheLinePad
  49. HasFP bool // Floating-point instruction set (always available)
  50. HasASIMD bool // Advanced SIMD (always available)
  51. HasEVTSTRM bool // Event stream support
  52. HasAES bool // AES hardware implementation
  53. HasPMULL bool // Polynomial multiplication instruction set
  54. HasSHA1 bool // SHA1 hardware implementation
  55. HasSHA2 bool // SHA2 hardware implementation
  56. HasCRC32 bool // CRC32 hardware implementation
  57. HasATOMICS bool // Atomic memory operation instruction set
  58. HasFPHP bool // Half precision floating-point instruction set
  59. HasASIMDHP bool // Advanced SIMD half precision instruction set
  60. HasCPUID bool // CPUID identification scheme registers
  61. HasASIMDRDM bool // Rounding double multiply add/subtract instruction set
  62. HasJSCVT bool // Javascript conversion from floating-point to integer
  63. HasFCMA bool // Floating-point multiplication and addition of complex numbers
  64. HasLRCPC bool // Release Consistent processor consistent support
  65. HasDCPOP bool // Persistent memory support
  66. HasSHA3 bool // SHA3 hardware implementation
  67. HasSM3 bool // SM3 hardware implementation
  68. HasSM4 bool // SM4 hardware implementation
  69. HasASIMDDP bool // Advanced SIMD double precision instruction set
  70. HasSHA512 bool // SHA512 hardware implementation
  71. HasSVE bool // Scalable Vector Extensions
  72. HasASIMDFHM bool // Advanced SIMD multiplication FP16 to FP32
  73. _ CacheLinePad
  74. }
  75. // PPC64 contains the supported CPU features of the current ppc64/ppc64le platforms.
  76. // If the current platform is not ppc64/ppc64le then all feature flags are false.
  77. //
  78. // For ppc64/ppc64le, it is safe to check only for ISA level starting on ISA v3.00,
  79. // since there are no optional categories. There are some exceptions that also
  80. // require kernel support to work (DARN, SCV), so there are feature bits for
  81. // those as well. The minimum processor requirement is POWER8 (ISA 2.07).
  82. // The struct is padded to avoid false sharing.
  83. var PPC64 struct {
  84. _ CacheLinePad
  85. HasDARN bool // Hardware random number generator (requires kernel enablement)
  86. HasSCV bool // Syscall vectored (requires kernel enablement)
  87. IsPOWER8 bool // ISA v2.07 (POWER8)
  88. IsPOWER9 bool // ISA v3.00 (POWER9)
  89. _ CacheLinePad
  90. }
  91. // S390X contains the supported CPU features of the current IBM Z
  92. // (s390x) platform. If the current platform is not IBM Z then all
  93. // feature flags are false.
  94. //
  95. // S390X is padded to avoid false sharing. Further HasVX is only set
  96. // if the OS supports vector registers in addition to the STFLE
  97. // feature bit being set.
  98. var S390X struct {
  99. _ CacheLinePad
  100. HasZARCH bool // z/Architecture mode is active [mandatory]
  101. HasSTFLE bool // store facility list extended
  102. HasLDISP bool // long (20-bit) displacements
  103. HasEIMM bool // 32-bit immediates
  104. HasDFP bool // decimal floating point
  105. HasETF3EH bool // ETF-3 enhanced
  106. HasMSA bool // message security assist (CPACF)
  107. HasAES bool // KM-AES{128,192,256} functions
  108. HasAESCBC bool // KMC-AES{128,192,256} functions
  109. HasAESCTR bool // KMCTR-AES{128,192,256} functions
  110. HasAESGCM bool // KMA-GCM-AES{128,192,256} functions
  111. HasGHASH bool // KIMD-GHASH function
  112. HasSHA1 bool // K{I,L}MD-SHA-1 functions
  113. HasSHA256 bool // K{I,L}MD-SHA-256 functions
  114. HasSHA512 bool // K{I,L}MD-SHA-512 functions
  115. HasSHA3 bool // K{I,L}MD-SHA3-{224,256,384,512} and K{I,L}MD-SHAKE-{128,256} functions
  116. HasVX bool // vector facility
  117. HasVXE bool // vector-enhancements facility 1
  118. _ CacheLinePad
  119. }
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